Known programmable DMA adapters and controllers are programmed by descriptors (or "descriptor blocks") prepared by a processor or microprocessor, and operate in response to such descriptors to control data transfers between an addressable memory system and peripheral devices; usually, over a bus that is accessible to multiple devices. Such adapters operate in a direct memory access mode; that is, they directly control memory addressing and control functions for each cycle of memory access. They also may operate as bus masters.
Information defining a series of data transfer operations relative to a group of contiguous memory address locations is usually contained in a single descriptor. Adapters which control multiple data transfer channels receive separate channel descriptor blocks (or CDB's) for each channel.
The memory and peripheral devices may be connected either directly, via a single bus, or indirectly via separate "memory bus" and "device bus" paths that are joined by the adapter. In the direct connection configuration, the data that is transferred propagates directly between the memory and devices, whereas in the indirect connection configuration it is buffered in internal registers or local memory in the adapter. In both configurations, system throughput is dependent upon how efficiently the adapter, devices and bus path(s) are used. Accordingly, it is desirable to minimize periods in which the adapter and devices are placed in "forced" states of idleness when new data transfer operations are being initiated.
CDB's defining successive data transfers in one adapter channel may be dispatched to the adapter either concurrently or sequentially, at random times. CDB's in a concurrently dispatched set are explicitly chained when dispatched; e.g., by an address pointer, in each CDB other than the last one in the set, defining the memory location of the next CDB in the set. Accordingly, the adapter usually operates without processor intervention or assistance to successively retrieve and process all of the CDB's in a concurrently dispatched/chained set.
As described in Related Patent Application 2, cited above, CDB's that are dispatched sequentially may also be handled as an implicitly or virtually chained set, i.e., they may be successively retrieved and processed by the adapter without processor intervention or assistance, but with the adapter creating and managing the chaining linkages between successively dispatched CDB's. In this mode of adapter operation, the adapter creates and manages linked list channel queues (separate queues for each channel), for handling dispatched CDB's that can not be immediately retrieved and processed. Each queue contains "head" and "tail" pointer information defining locations of first and last CDB to be processed; the first CDB being the one to be processed next, when the adapter is ready to do so, and the last CDB being the CDB last dispatched to the respective adapter channel. As CDB's are entered into "tail end" positions in such queues, the adapter inserts chaining pointers into the preceding CDB entry (via a memory Write operation), and as a next CDB is retrieved for processing, the chaining pointer link in that CDB becomes the new head pointer for the respective queue.
With this virtual chaining arrangement, the adapter and devices can be kept efficiently employed by the host processor system without "hogging" memory; i.e., the host processor need only allocate memory space for each CDB and the associated data transfer when the CDB is dispatched, whereas when CDB's are concurrently dispatched in an explicitly chained set, the host system must allocate memory space for all CDB's and all respective data transfers when the concurrent dispatch is effected.
Furthermore, with the virtual chaining arrangement the delegation of chaining queue management responsibilities to the adapter effectively reduces the processing load of the host system and frees the latter to perform other tasks which it might not otherwise be able to handle. It also enhances system productivity in other ways, since it allows for dispatching of CDB's while the adapter and devices are actively handling other data transfers; where batch dispatching of chained CDB's might require the adapter and devices to be in idle states of unpredictable duration while they are being prepared for a new descriptor chain. This idling requirement is needed primarily because the processor has no instantaneous awareness of the active state of any data transfer (receiving its state information through interruption handling processes that are entirely asynchronous to the transfer processes), and can not risk obstructing a current data transfer process while carrying out the dispatching procedure (with associated risk of causing an overrun or underrun in the respective transfer process).
Even with the virtual chaining capability described in Reference Patent Application 2, cited above, there are situations in which the processor would be unable to sequentially dispatch descriptors without having the adapter in an idle state. For example, if the adapter and a device are currently carrying out a half-duplex data transfer, and the next descriptor to be dispatched calls for the adapter and the same device to transfer data in the opposite direction, it could be necessary for the processor to change operating states of the device and/or adapter (to effect path reversal) before dispatching the next descriptor. However, this state change could not be carried out until the processor has determined that the adapter and device have completed their current transfer tasks; and since the interruption process by which the processor makes that determination may lag the actual completion event by an indefinite time, it is understood that in such situations the adapter and device could sit idle for a long time only because of this lack of processor coordination.
The present invention seeks to provide an adapter mechanism that effectively would eliminate this type of processing "roadblock", and thereby improve system efficiency. With this mechanism, an adapter could perform device reconfiguration functions, that ordinarily would be handled by a processor, and handle the performance in coordination with its other tasks so as to eliminate idleness or discontinuities in its activities.